Packaging an integrated circuit is typically the final stage of semiconductor device fabrication. During packaging, a semiconductor die, which represents the core of a semiconductor device, is encased in a housing that protects the die against physical damage and corrosion. For example, semiconductor dies are commonly mounted on a copper substrate, using solder alloy reflow, conductive epoxy, and the like. The mounted semiconductor die is often then encapsulated within an epoxy compound.
As the power requirements of semiconductor devices have increased in recent years, larger semiconductor dies, sometimes referred to as “large area semiconductor dies,” have become necessary for providing correspondingly greater levels of current handling. In some cases, such as in TVS diode applications, multiple large area dies must be connected in series in a stacked configuration to provide a sufficiently high breakdown voltage. A fundamental problem associated with packaging large area semiconductor dies is the effect of mismatches between the coefficient of thermal expansion (CTE) of the dies and the substrates upon which the dies are mounted. Such mismatches result in dies and their substrates expanding and contracting at different rates and to different degrees when exposed to thermal cycling conditions. As such, the dies are subjected to thermal stress. As will be appreciated, the semiconductor dies (e.g., silicon dies, or the like) are relatively brittle. Accordingly, they often crack or break as a result of such thermal stress, which causes device failure.
The amount of thermal stress is generally proportional to the amount of bonded surface area (i.e., the area of bonded, surface-to-surface contact) between a die and its substrate. Large area semiconductor dies, which share more bonded surface area with their substrates relative to smaller dies, are therefore more prone to cracking as a result of significant thermal stresses sustained during thermal cycling. For example, FIG. 1 shows a finite element analysis (FEA) of a stack 100 of three large area semiconductor dies 110 that are reflowed directly to a copper substrate 120. Approximately 100% of the surface area of the dies 110 is bonded to the substrate 120. It is apparent from this view that the dies 110 are placed under a significant amount of thermal stress.
In order to mitigate CTE mismatch problems, buffer layers formed of materials having CTEs similar to that of silicon are sometimes mounted between semiconductor dies and the substrates (e.g., copper). For example, in cases where electrical isolation is desired between a semiconductor die and a substrate, the buffer layer may be formed of a ceramic material such as alumina or AlNi. In cases where electrical isolation is not desired, the buffer layer may be formed of a conductive material such as molybdenum or tungsten alloy. Such materials are generally very expensive and are difficult to apply in conventional integrated circuit assembly operations.
In view of the forgoing, it would be desirable to provide a low cost, easily implemented package for large area semiconductor dies that does not subject dies to significant thermal stresses during thermal cycling.